Examples in which an A/D converter is used according to the related art are disclosed in Patent Documents 1 to 4. First, the configuration and operation of an A/D converter disclosed in Patent Document 1 will be described.
FIG. 24 is a diagram illustrating the configuration of a MOS sensor that uses an A/D converter according to a first related art disclosed in Patent Document 1. The MOS sensor includes an A/D conversion circuit 1106 that includes a comparator 1107 and a digital memory 1108 in each column of pixels 1101. A digital (binary) value output from a counter 1104 is input to a D/A conversion circuit (hereinafter, referred to as a DAC) 1105. The DAC 1105 generates a ramp voltage (ramp wave) 1122 in accordance with the input digital value and outputs the ramp voltage (ramp wave) 1122 as a reference signal to one of input units of the comparator 1107. The output of the counter 1104 is distributed to the digital memories 1108 in the respective columns via the binary-to-gray code converter 1115. A pixel signal is input as an analog signal to be subjected to A/D conversion from the pixel 1101 to the other of the input units of the comparator 1107 of each A/D conversion circuit 1106 via a read signal line 1103.
Next, an A/D conversion process according to the first related art will be described. First, the counter 1104 starts counting a value from an initial value in synchronization with a clock signal 1121 input from a clock generation circuit 1120 and the DAC 1105 starts generating the ramp voltage (ramp wave) 1122. Then, a signal read from the pixels 1101 in each column and the common ramp voltage (ramp wave) 1122 varying in synchronization with the counted value of the counter 1104 are input to the comparator 1107 at each column. The counted value of the counter 1104 is distributed to the digital memories 1108 in parallel to the ramp voltage. When a magnitude relation between two input signals in the comparator 1107 at a given column is exchanged, an output voltage of the comparator 1107 is inverted and the digital memory 1108 at this column retains the counted value. Since the ramp voltage (ramp wave) 1122 input into the comparator 1107 and the counted value input into the digital memory 1108 are synchronized with each other, the signal read from the pixel is A/D converted into a value (digital value) retained in the digital memory by the above-described process.
The A/D conversion scheme described above is a kind of scheme called counting ADC (counting A/D conversion) according to general classification of the A/D conversion in a scheme called ramp-type A/D conversion (Ramp Run-up ADC). Using the ramp voltage (ramp wave) as a reference signal is equivalent to converting an analog signal potential from a pixel into the length of time. Further, since the A/D conversion is realized by measuring the length of time by the use of the clock signal of a fixed frequency, this term is used.
In an A/D converter according to the second related art disclosed in Patent Documents 2 to 4, resolution can be further improved by setting the counted value of the counter 1104 to high-order bits, generating a multi-phase clock by delaying the phase of a clock (or a clock output from the counter) input to the counter, and setting the logic state to the low-order bits.
For example, when the A/D conversion of 10 bits is realized by the A/D converter according to the first related art, it is necessary to perform counting by the number of gray scales of 10 bits (that is 1024 times) in the comparison between an analog signal to be subjected to the A/D conversion and the ramp voltage (ramp wave) generated by a DAC.
Here, an imager used as a specific device using the A/D converter in a digital still camera (DSC) or the like will be exemplified. In regard to a specific specification, the number of pixels is 20 million and the frame rate is 60 frame/sec. To facilitate the description, it is assumed that the pixel arrangement of 20 million pixels is an aspect ratio of 4000 rows×5000 columns and there is no blanking period for further simplification. Then, a read period of one row is 60 frame/sec×4000 rows/frame=240 Kline/sec. That is, a read rate of one row is 240 kHz. When the A/D converter according to the first related art is applied to this device, comparison of the number of gray scales 2^10=1024 times has to be performed in the read period of one row in the A/D conversion of 10 bits. Therefore, it is necessary to change the counted value of the counter outputting data to the digital memory at about 240 MHz which is about a thousand times the read rate of one row.
In this calculation, a wait period in which the A/D conversion circuit receives data from the pixels or a transmission period in which the result of the A/D conversion is output to a memory, that is, a period in which the comparison process as the A/D conversion is not performed, is not considered. Further, since an OB (Optical Black) pixel period or a blanking period is excluded, actually, the read rate of one row is a frequency higher than the estimated frequency.
Next, the read rate of one row will be calculated in the same way using the A/D converter according to the second related art. For example, it is assumed that 10 bits are composed of 8 high-order bits and 2 low-order bits. In the case of the high-order bits, the calculation is made by changing the counted value of the counter outputting data to the digital memory at about 60 MHz which is 256 times the read rate of one row. In the case of the low-order bits, a digital value is obtained by delaying the phase of a clock (a clock output from the counter) input to the counter by 0, π/4, π/2, and 3π/4 and retaining and encoding the logic state. Further, it is assumed that 10 bits are composed of 6 high-order bits and 4 low-order bits. In the case of the high-order bits, the calculation is made by changing the counted value of the counter outputting data to the digital memory at about 15 MHz which is 64 times the read rate of one row. In the case of the low-order bits, a digital value is obtained by delaying the phase of a clock (a clock output from the counter) input to the counter by 0, π/16, π/8, 3π/16, π/4, 5π/16, 3π/8, 7π/16, π/2, 9π/16, 5π/8, 11π/16, 3π/4, 13π/16, 7π/8, and 15π/16 and retaining and encoding the logic state.